Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Mulitplexed FPGA Synthesis
نویسندگان
چکیده
In this paper, we present a unified estimation technique to find the lower bounds on the number of LUT blocks and that of the micro-registers which can be obtained by any partitioning or synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. Some experimental results on lower bound estimation are shown and compared with the previous results published in the literature.
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